a-Si:H diodes have been optimized at IMT Neuchatel for the fabrication of TFA sensors for visible light [6], X-ray and particle sensing [7]. In this context, diodes with dark current Jdark as low as 1 pA/cm2 and corresponding TFA sensors with Jdark of 12 pA/cm2 (both at bias voltage of -1 V) have been fabricated [6]. The issues regarding the design of a-Si:H photodiodes and specifically the influence of the CMOS chip design/topology on the performances of the a-Si:H photodiodes have already been discussed in details [6, 8].In this paper, we will focus on the performance of TFA image sensors and will analyze the transient behavior of a-Si:H diodes. a-Si:H exhibits a continuous distribution of localized states in the band gap (more exactly of the pseudo gap, see Fig.

2).

This distribution comprises tails states due to the disorder present in the amorphous silicon and defect states due to Si dangling bonds. Any change in the polarization or of the illumination level of an a-Si:H diode will perturb the equilibrium between free carriers in the band and trapped carriers in the localized states leading to transient behavior of such device. The objective of this paper is to analyze those transients in test diodes and corresponding TFA imagers.Figure 2.Schematic band diagram of a-Si:H. The continuous state distribution in the pseudo gap, tail states and defect states, is acting as charge reservoir which can be filled-up and emptied during operation of a-Si:H photodiodes and is controlling the transient .

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Effect of carrier trapping and release in a-Si:H diode has already been investigated in previous studies and modeled by simple Shockley-Read statistics [9,10]. The present work focuses on the photocurrent decay kinetics of state-of-the-art a-Si:H diodes in TFA sensors, including simulations using a full description of a-Si:H state distribution.2.?Experimental Batimastat detailsSeveral imagers in using TFA technologies were fabricated by depositing (0.5-2 ��m thick) a-Si:H diode arrays both in the metal-i-p and in the n-i-p configurations on standard passivated CMOS chips as well as unpassivated ones covered with a common top 65 nm thick ITO electrode. These chips consisted in an array of 64��64 pixels, with a pixel lateral size of 33 ��m (passivated chip) or 38.

4 ��m (unpassivated) and a pitch of 40 ��m from Alcatel-Mitag 0.5 ��m MPW (multiple project wafer) technology. For half of the chips, pixels were connected within the CMOS chip to an individual charge integrator Anacetrapib while the other half was used to test other internal circuit designs and was not available for imaging. A fill factor of ��92% was achieved for the imager on unpassivated chips.